The invention relates to a digital memory circuit which contains at least two areas having a respective multiplicity of memory cells, disposed in a matrix form in rows and columns, for storing a respective binary data item. For each column, a primary sense amplifier is provided for sensing the data item stored in an addressed cell and for using a transfer switch which can be turned on by a column selection signal to connect a first wire in a two-wire local data line associated with the primary sense amplifier in question to a first logic potential and to connect a second wire in the local data line to a second logic potential when the sensed data item has the first binary value, and to connect the first wire to the second logic potential and to connect the second wire to the first logic potential when the sensed data item has the second binary value. Each local data line can be connected by a respective line circuit-breaker to a two-wire master data line which is associated with a respective local data line for each area in the memory bank and is routed to the input connections of a secondary sense amplifier individually associated with it. Precharging devices are provided for temporarily equalizing both wires in all the local data lines to a potential situated between the first and second logic potentials and for temporarily equalizing both wires in all the master data lines to the first logic potential before a transfer switch is turned on. A preferred but not exclusive area of application for the invention is DRAM memories.
In digital data stores, the binary memory cells in each memory bank are frequently combined into a plurality of separate areas which each have a dedicated set of sense amplifiers, each of which is responsible for a subset of the cells in the area in question. Normally, the cells in each memory area form a matrix containing rows and columns, and each column has an associated sense amplifier. Each sense amplifier is connected by an associated bit line to all the memory cells in the column in question. Each row can be selectively addressed by activating an associated word line. The corresponding activation signal is derived in a word line decoder (row decoder) from the row address for the memory cell that is to be read. The result of activation is that each cell in the row in question communicates its memory content to the sense amplifier that is associated with the column in question, and the sense amplifier then generates an amplified signal that represents the binary value of the stored data item. This representation is then transferred, by turning on a transfer switch individually associated with the sense amplifier, to an associated local data line which can be connected by a line circuit-breaker to an associated master data line which is common to all the memory areas in the bank, in order to transfer the binary representation to a secondary sense amplifier and to amplify it there for the purpose of outputting the data item.
The transfer switches are controlled by column selection signals that are derived by a column decoder from the column address for the memory cells that are to be read. The column selection signals are supplied to all the memory areas together.
In many cases, particularly in large memory banks having a very large number of columns in each memory area, the total number n of columns in each area is split into m adjacent groups, each of which contains k=n/m columns and occupies a corresponding segment in the memory area. Accordingly, the local data lines are also segmented. Each group (that is to say each segment) can in turn be split into p adjacent subgroups, each of which contains q=k/p columns, with all the transfer switches associated with the sense amplifiers in the same subgroup being respectively actuated by a common column selection signal associated with the subgroup. In order to forward the data transferred by the q transfer switches in the same respective subgroup separately from one another in such cases, each segment has q local data lines provided along it, each of which is connected to precisely one individually assigned transfer switch for each subgroup of the columns in the segment in question. If q=1, a dedicated column selection signal is generated for each column and hence for each transfer switch.
In line with the number m of segments, m bundles of master data lines are provided. Each of the bundles contains q master data lines associated with the q local data lines of a respective segment in all the memory areas.
Normally, the bit lines, the local data lines and the master data lines are two-wire lines. In this regard, each primary sense amplifier is configured to have a symmetrical output. If a memory cell content which a primary sense amplifier senses corresponds to a data item with the first binary value, the output of the amplifier produces a potential difference whose polarity indicates the binary value of the data item stored in the cell. If the cell content corresponds to a data item with the first binary value, then one output connection of the amplifier changes to a first defined logic potential and the other output connection changes to a second defined logic potential. If the cell content corresponds to a data item with the second binary value, then the two logic potentials on the output connections of the amplifier appear the other way round. By virtue of the transfer switch being turned on when the line circuit-breaker is on, the output potentials of the sense amplifier are applied to the wires in the associated local data line and arrive, via the line circuit-breaker, on the wires in the associated master data line, so that they produce a potential difference there which represents the sensed data item. The secondary sense amplifier is therefore in the form of a differential amplifier having a symmetrical input. All the supply potentials of the primary and secondary sense amplifiers are symmetrical around the center between the two logic potentials and are close to one or the other logic potential.
In the quiescent state of the memory circuit, before a read or write mode is initiated, the wires in all the bit lines are equalized to a particular potential which is normally situated centrally between the two logic potentials. The wires in all the local data lines are likewise equalized to this potential, specifically for the following reason: during subsequent column selection, the selected transfer switches are, of course, on not just in that memory area which contains the activated word line, but also in all the other memory areas whose bit lines have all retained the equalization potential. The aforementioned equalization of the local data lines to the potential results in that unnecessary charging currents are avoided in the other memory areas.
In the quiescent state of the memory circuit, the wires in all the master data lines are likewise equalized to a particular potential. For the second-mentioned equalization potential, one of the two logic potentials is chosen, specifically that which corresponds or comes close to the load-side supply potential of the secondary sense amplifier. This is because the amplifier then remains in the linear region of the amplifier characteristic curve when the input connections are actuated using the aforementioned potential difference representing the sensed data item.
Upon initiation of a read or write mode, the wires in all the bit lines and local data lines are isolated from the source of the associated equalization potential, so that the wires in those instances of the lines which are selected for access can assume the data-specific potential differences.
In memory circuits based on the prior art, each line circuit-breaker is a two-terminal switch having an external control connection for applying a turn-on signal which turns on the switch and keeps it on for the duration of this signal. All line circuit-breakers associated with the same memory area are controlled together in the prior art. Since the row address for an addressed memory cell also identifies the respective memory area, a line circuit-breaker selection device based on the prior art operates on the basis of the row address decoded in the word line decoder in order to transfer the turn-on signal simultaneously to all the line circuit-breakers in the memory area which contains the addressed row.
The aforementioned turn-on signal for the line circuit-breakers requires a relatively large amount of current, particularly when it is xe2x80x9cboostedxe2x80x9d, that is to say is operated at increased voltage, in accordance with the customary prior art. In addition, in the described cases of segmentation of the individual memory areas in the prior art, a large amount of current is required for charge reversal on the local data lines. This is because when the line circuit-breakers in a memory area are turned on, which normally occurs before transfer switches in the memory area in question are turned on, both wires in all the local data lines of all the segments of the memory area in question first change from their equalization potential, which is situated centrally between the two logic potentials, to the equalization potential for the master data lines, which is the same as one of the logic potentials. To this end, the source of the equalization potential for the master data lines needs to deliver a large amount of charging current.
It is accordingly an object of the invention to provide a digital memory circuit having a plurality of memory areas that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has a reduced current consumption during operation of the memory circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, a digital memory circuit. The memory circuit includes at least one memory bank containing at least two areas having a respective multiplicity of memory cells, disposed in a matrix form in rows and columns, for storing binary data. Primary sense amplifiers are provided, and one of the primary sense amplifiers is provided for each of the columns for sensing the binary data stored in an addressed memory cell. Two-wire local data lines each having a first wire and a second wire, are provided. Transfer switches are provided, and a respective transfer switch is connected between a respective two-wire local data line and a respective primary sense amplifier. The respective transfer switch receives and is turned on by a column selection signal. The respective primary sense amplifier uses the respective transfer switch to connect the first wire in the respective two-wire local data line to a first logic potential and to connect the second wire to a second logic potential when a sensed data item has a first binary value, and to connect the first wire to the second logic potential and to connect the second wire to the first logic potential when the sensed data item has a second binary value. Two-wire master data lines are provided and each have a first wire and a second wire and are associated with the respective two-line local data line for each of the areas of the memory bank.
Line circuit-breakers are used, and a respective line circuit-breaker is connected between the respective two-line local data line and a respective two-wire master data line.
Secondary sense amplifiers are used and have inputs connected to the two-wire master data lines. Precharging devices are connected to and temporarily equalize the first and second wires in all of the two-wire local data lines to a potential situated between the first and second logic potentials and for temporarily equalizing the first and second wires in all of the two-line master data lines to the first logic potential before the transfer switches are turned on. Each of the line circuit-breakers contain switching devices for sensing electrical potentials appearing on the first and second wires in the respective two-wire local data line and in the respective two-wire master data line and, depending on a sensing result, if one of the first and second two wires of the respective two-wire local data line is at the second logic potential, the respective line circuit-breaker transfers the second logic potential to an associated one of the first and second wires of the two-wire master data line, and if one of the first and second wires of the respective two-line master data line is at the second logic potential, the respective two-line master data line transfers the second logic potential to an associated one of the first and second wires of the respective two-wire local data line.
The inventive configuration of the line circuit-breakers thus ensures that the line circuit-breakers are turned on autonomously, without the need for external control voltages, only on those local data lines which are used to effect a write or read mode. In the event the memory areas have a segmented configuration, the charging current consumption from the source of the equalization potential for the master data lines is lower than in conventional practice, because not all of the local data lines in the memory area in question are charged to the equalization potential for the master data lines, but rather only the local data lines of the selected segments. Since it is not necessary to apply any external actuating voltages for the line circuit-breakers, there is no longer any current consumption for this purpose, which results in a savings on current is also achieved in the case of unsegmented memory areas.
In accordance with an added feature of the invention, the switching devices of each of the line circuit-breakers further contain a first field effect transistor having a channel connected between the first wire of the respective two-line local data line and the first wire of the respective two-wire master data line and a gate connected to the second wire of the respective two-wire local data line. A second field effect transistor is provided and has a channel connected between the second wire of the respective two-wire local data line and the second wire of the respective two-wire master data line and a gate connected to the first wire of the respective two-wire local data line. A third field effect transistor is provided and has a channel connected between the first wire of the respective two-wire local data line and the first wire of the respective two-wire master data line and a gate connected to the second wire of the respective two-wire master data line. A fourth field effect transistor is provided and has a channel connected between the second wire of the respective two-wire local data line and the second wire of the respective two-wire master data line and a gate connected to the first wire of the respective two-wire local data line. The first, second, third and fourth field effect transistors have a conductivity type such that the first, second, third and fourth field effect transistors transfer the second logic potential when the gate is at the first logic potential.
In accordance with an additional feature of the invention, wherein and depending on the sensing result, if one of the first and second wires of the respective two-wire master data line is at the first logic potential, the switching devices contained in each of the line circuit-breakers transfer the first logic potential to an associated one of the first and second wires of the respective two-line local data line.
In accordance with a further feature of the invention, the switching devices of each of the line circuit-breakers further contain a fifth field effect transistor having a channel connected between the first wire of the respective two-wire local data line and the first wire of the respective two-line master data line and a gate connected to the second wire of the respective two-line master data line. A sixth field effect transistor is provided and has a channel connected between the second wire of the respective two-wire local data line and the second wire of the respective two-wire master data line and a gate connected to the first wire of the respective two-wire master data line. The fifth and sixth field effect transistors are of a further conductivity type being opposite the conductivity type of the first, second, third, and fourth field effect transistors.
In accordance with a concomitant feature of the invention, the columns in each of the areas of the memory bank form at least two adjacent groups, and each of the at least two adjacent groups occupies a separate segment of a respective area. Each of the two-wire local data lines is associated with precisely one of the segments of precisely one area of the memory bank. Each of the two-line master data lines is associated with precisely one segment of each area of the memory bank.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a digital memory circuit having a plurality of memory areas, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.